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mos integrated circuit pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y v850es/sa2 tm , v850es/sa3 tm 32-bit single-chip microcontrollers document no. u15436ej1v0pm00 (1st edition) date published june 2001 n cp(k) printed in japan preliminary product information the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 description the pd703201, 703201y, 70f3201, and 70f3201y (v850es/sa2), pd703204, 703204y, 70f3204, and 70f3204y (v850es/sa3) are products in the v850 family tm of 32-bit single-chip microcontrollers, and include peripheral functions such as rom/ram, timer/counters, serial interfaces, an a/d converter, a d/a converter, and a dma controller. in addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the v850es/sa2 and v850es/sa3 include instructions suited to digital servo control applications such as multiplication instructions executed via a hardware multiplier, saturation instructions, and bit manipulation instructions. as a real-time control system, this device provides a high-level cost performance ideal for ultra-low-power dvc and portable audio applications. detailed function descriptions are provided in the following user?s manuals. be sure to read them before designing. v850es/sa2, v850es/sa3 user?s manual hardware: to be prepared v850es user?s manual architecture: to be prepared features { number of instructions: 83 { minimum instruction execution time: 59 ns (@ 17 mhz operation with main system clock (f xx )) 74 ns (@ 13.5 mhz operation with main system clock (f xx )) { general-purpose registers: 32 bits 32 registers { instruction set: signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { memory space: 64 mb linear address space memory block division function: 2 mb, 2 mb, 4 mb, 8 mb = total four blocks { external bus interface: 16-bit data bus address bus: separate output enabled { internal memory mask rom: 256 kb ( pd703201, 703201y, 703204, 703204y) flash memory: 256 kb ( pd70f3201, 70f3201y, 70f3204, 70f3204y) ram: 16 kb { interrupts and exceptions non-maskable interrupts: 2 sources maskable interrupts: 38 sources ( pd703201, 70f3201) 39 sources ( pd703201y, 70f3201y) 39 sources ( pd703204, 70f3204) 40 sources ( pd703204y, 70f3204y) software exceptions: 32 sources exception trap: 1 source { i/o lines total: 82 (v850es/sa2) 102 (v850es/sa3) { timer/counters 16-bit timer: 2 channels 8-bit timer: 4 channels { real-time counter (for watch): 1 channel { watchdog timer: 1 channel
preliminary product information u15436ej1v0pm 2 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y { serial interface (sio) asynchronous serial interface (uart): 2 channels clocked serial interface (csi): 4 channels (v850es/sa2), 5 channels (v850es/sa3) i 2 c bus interface: 1 channel ( pd703201y, 703204y, 70f3201y, 70f3204y) { a/d converter: 10-bit resolution 12 channels (v850es/sa2) 10-bit resolution 16 channels (v850es/sa3) { d/a converter: 8-bit resolution 2 channels { dma controller: 4 channels { power save functions: halt/idle/stop/backup modes { rom correction: four points can be corrected { packages: 100-pin plastic lqfp (14 14) (v850es/sa2) 121-pin plastic fbga (12 12) (v850es/sa3) applications { low-power portable devices dvcs, portable audios ordering information part number package internal rom pd703201gc- -8eu pd703201ygc- -8eu pd703204f1- -ea6 pd703204yf1- -ea6 pd70f3201gc-8eu pd70f3201ygc-8eu pd70f3204f1-ea6 pd70f3204yf1-ea6 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 121-pin plastic fbga (12 12) 121-pin plastic fbga (12 12) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic lqfp (fine pitch) (14 14) 121-pin plastic fbga (12 12) 121-pin plastic fbga (12 12) 256 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 256 kb (flash memory) 256 kb (flash memory) 256 kb (flash memory) 256 kb (flash memory) remark indicates rom code suffix.
preliminary product information u15436ej1v0pm 3 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y pin configuration ? ? ? ? v850es/sa2 100-pin plastic lqfp (fine-pitch) (14 14) pd703201gc- -8eu pd703201ygc- -8eu pd70f3201gc-8eu pd70f3201ygc-8eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 p05/intp4 p04/intp3/ti5 p03/intp2/ti4 p02/intp1/ti3 p01/intp0/ti2 p46/intp11/to1 p45/intp10/ti1/tclr1 p44/intp01/to0 p43/intp00/ti0/tclr0 p42/sck0/scl note 1 p41/so0/sda note 1 p40/si0 pdh5/a21 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p96/a6/to4 p97/a7/to5 p98/a8/rxd1 p99/a9/txd1 p910/a10/si2 p911/a11/so2 p912/a12/sck2 p913/a13/si3 p914/a14/so3 p915/a15/sck3 ev ss ev dd pcs0/cs0 pcs1/cs1 pcs2/cs2 pcs3/cs3 pcm0/wait pcm1/clkout pcm2/hldak pcm3/hldrq pct0/wr0 pct1/wr1 pct4/rd pct5 pct6/astb 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 av ref0 av dd av ss p80/ano0 p81/ano1 av ref1 p00/nmi p30/si1/rxd0 p31/so1/txd0 p32/sck1 v dd v ss x1 x2 reset xt1 xt2 v ss bu v dd bu p90/a0 p91/a1 p92/a2/intp5 p93/a3/intp6 p94/a4/to2 p95/a5/to3 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 ev dd ev ss ic/flmd0 notes 2, 3 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 note 2 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 pct7 notes 1. scl and sda are valid only for the pd703201y and 70f3201y. 2. flmd0 and flmd1 are valid only for the pd70f3201 and 70f3201y. 3. ic: connect directly to v ss ( pd703201, 703201y). flmd0: connect to v ss in normal mode ( pd70f3201, 70f3201y).
preliminary product information u15436ej1v0pm 4 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y ? ? ? ? v850es/sa3 121-pin plastic fbga (12 12) pd703204f1- -ea6 pd70f3204f1-ea6 pd703204yf1- -ea6 pd70f3204yf1-ea6 (1/2) top view bottom view nmlkjhgfedcba abcdefghjklmn 13 12 11 10 9 8 7 6 5 4 3 2 1 pin no. pin name pin no. pin name pin no. pin name a1 p70/ani0 b8 pcd3 d2 av ref1 a2 p71/ani1 b9 p02/intp1/ti3 d3 p00/nmi a3 p73/ani3 b10 p46/intp11/to1 d11 pdh0/a16 a4 p713/ani13 b11 p42/sck0/scl note d12 pdh2/a18 a5 p76/ani6 b12 p40/si0 d13 pdh1/a17 a6 p78/ani8 b13 pdh4/a20 e1 p30/si1/rxd0 a7 p711/ani11 c1 p80/ano0 e2 p31/so1/txd0 a8 p04/intp3/ti5 c2 av ss e3 p32/sck1 a9 pcd2 c3 p74/ani4 e11 pdl14/ad14 a10 p45/intp10/ti1/tclr1 c4 p714/ani14 e12 pdh6/a22 a11 p43/intp00/ti0/tclr0 c5 p715/ani15 e13 pdl15/ad15 a12 p41/so0/sda note c6 p79/ani9 f1 v ss a13 pdh5/a21 c7 p05/intp4 f2 x1 b1 av dd c8 p03/intp2/ti4 f3 v dd b2 av ref0 c9 pcd1 f11 pdl11/ad11 b3 p72/ani2 c10 p01/intp0/ti2 f12 pdl13/ad13 b4 p712/ani12 c11 p44/intp01/to0 f13 pdl12/ad12 b5 p75/ani5 c12 pdh3/a19 g1 reset b6 p77/ani7 c13 pdh7/a23 g2 xt1 b7 p710/ani10 d1 p81/ano1 g3 x2 note scl and sda are valid only for pd703204y and 70f3204y. remark connect the d4 pin directly to v ss .
preliminary product information u15436ej1v0pm 5 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (2/2) pin no. pin name pin no. pin name pin no. pin name g11 ev ss k13 pdl3/ad3 m7 pcs4 g12 pdl10/ad10 l1 p93/a3/intp6 m8 pcm0/wait g13 ev dd l2 p94/a4/to2 m9 pcm2/hldak h1 v ss bu l3 p911/a11/so2 m10 pct3 h2 v dd bu l4 p914/a14/so3 m11 pct4/rd h3 xt2 l5 p915/a15/sck3 m12 pct7 h11 pdl8/ad8 l6 ev dd m13 pdl0/ad0 h12 ic/flmd0 notes 1, 2 l7 pcs0/cs0 n1 p96/a6/to4 h13 pdl9/ad9 l8 pcs2/cs2 n2 p98/a8/rxd1 j1 p20/si4 l9 pcm4 n3 p910/a10/si2 j2 p91/a1 l10 pct2 n4 p912/a12/sck2 j3 p90/a0 l11 pct0/wr0 n5 pcs7 j11 pdl5/ad5/flmd1 note 1 l12 pdl1/ad1 n6 pcs6 j12 pdl7/ad7 l13 pdl2/ad2 n7 pcs1/cs1 j13 pdl6/ad6 m1 p95/a5/to3 n8 pcs3/cs3 k1 p22/sck4 m2 p97/a7/to5 n9 pcm5 k2 p92/a2/intp5 m3 p99/a9/txd1 n10 pcm3/hldrq k3 p21/so4 m4 p913/a13/si3 n11 pct1/wr1 k11 pcm1/clkout m5 ev ss n12 pct5 k12 pdl4/ad4 m6 pcs5 n13 pct6/astb notes 1. flmd0 and flmd1 are valid only for pd70f3204y and 70f3204y. 2. ic: connect directly to v ss ( pd703204, 703204y). flmd0: connect to v ss in normal mode ( pd70f3204, 70f3204y).
preliminary product information u15436ej1v0pm 6 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y pin identification a0 to a23: ad0 to ad15: adtrg: ani0 to ani15: ano0, ano1: astb: av dd : av ref0 , av ref1 : av ss : clkout: cs0 to cs3: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: ic: intp0 to intp6: intp00, intp01,: intp10, intp11 nmi: p00 to p05: p20 to p22: p30 to p32: p40 to p46: p70 to p715: p80, p81: p90 to p915: address bus address/data bus ad trigger input analog input analog output address strobe analog v dd analog reference voltage analog v ss clock output chip select power supply for port ground for port flash programming mode hold acknowledge hold request internally connected interrupt request from peripherals interrupt request to timer non-maskable interrupt request port 0 port 2 port 3 port 4 port 7 port 8 port 9 pcd1 to pcd3: pcm0 to pcm5: pcs0 to pcs7: pct0 to pct7: pdh0 to pdh7: pdl0 to pdl15: rd: reset: rxd0, rxd1: sck0 to sck4: scl: sda: si0 to si4: so0 to so4: tclr0, tclr1: ti0 to ti5: to0 to to5: txd0, txd1: v dd : v dd bu: v ss : v ss bu: wait: wr0: wr1: x1, x2: xt1, xt2: port cd port cm port cs port ct port dh port dl read reset receive data serial clock serial clock serial data serial input serial output timer clear input timer input timer output transmit data power supply power supply for backup ground ground for backup wait write strobe low level data write strobe high level data crystal for main clock crystal for subclock
preliminary product information u15436ej1v0pm 7 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y internal block diagram ? ? ? ? v850es/sa2 nmi intp00, intp01, intp10, intp11 to0, to1 sio ti0, ti1 tclr0, tclr1 so0 to so3 si0 to si3 sck0 to sck3 intp0 to intp6 intc timer/counter 16-bit timer: 2 ch to2 to to5 ti2 to ti5 timer/counter 8-bit timer: 4 ch txd0, txd1 rxd0, rxd1 uart: 2 ch sda note 2 scl note 2 i 2 c note 2 : 1 ch dmac watchdog timer real-time counter note 1 ram rom 16 kb pc general-purpose registers 32-bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 cs0 to cs3 a0 to a21 ad0 to ad15 ic note 3 flmd0 note 4 , flmd1 note 4 ports cg rg a/d converter d/a converter pcs0 to pcs3 pcm0 to pcm3 pct0, pct1, pct4 to pct7 pdh0 to pdh5 pdl0 to pdl15 p90 to p915 p80, p81 p70 to p711 p40 to p46 p30 to p32 p00 to p05 ano0, ano1 av ref1 av dd av ref0 av ss ani0 to ani11 clkout x1 x2 xt1 xt2 reset v dd v ss v dd bu v ss bu ev dd ev ss instruction queue bcu csi: 4 ch rom correction notes 1. pd703201, 703201y: 256 kb (mask rom) pd70f3201, 70f3201y: 256 kb (flash memory) 2. applies to the pd703201y and 70f3201y only. 3. applies to the pd703201 and 703201y only. 4. applies to the pd70f3201 and 70f3201y only.
preliminary product information u15436ej1v0pm 8 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y ? ? ? ? v850es/sa3 nmi intp00, intp01, intp10, intp11 to0, to1 sio ti0, ti1 tclr0, tclr1 so0 to so4 si0 to si4 sck0 to sck4 intp0 to intp6 intc timer/counter 16-bit timer: 2 ch to2 to to5 ti2 to ti5 timer/counter 8-bit timer: 4 ch txd0, txd1 rxd0, rxd1 uart: 2 ch sda note 2 scl note 2 i 2 c note 2 :1 ch dmac watchdog timer real-time counter note 1 ram rom 16 kb pc general-purpose registers 32-bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 cs0 to cs3 a0 to a23 ad0 to ad15 ic note 3 flmd0 note 4 , flmd1 note 4 ports cg rg a/d converter d/a converter pcs0 to pcs7 pcm0 to pcm5 pct0 to pct7 pdh0 to pdh7 pdl0 to pdl15 pcd1 to pcd3 p90 to p915 p80, p81 p70 to p715 p40 to p46 p30 to p32 p20 to p22 p00 to p05 ano0, ano1 av ref1 av dd av ref0 av ss ani0 to ani15 clkout x1 x2 xt1 xt2 reset v dd v ss v dd bu v ss bu ev dd ev ss instruction queue bcu csi: 5 ch rom correction notes 1. pd703204, 703204y: 256 kb (mask rom) pd70f3204, 70f3204y: 256 kb (flash memory) 2. applies to the pd703204y and 70f3204y only. 3. applies to the pd703204 and 703204y only. 4. applies to the pd70f3204 and 70f3204y only.
preliminary product information u15436ej1v0pm 9 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y contents 1. pin functions ............................................................................................................... .................11 1.1 port pins ................................................................................................................... ................................ 11 1.2 non-port pins............................................................................................................... ............................ 14 1.3 pin i/o circuits and recommended connection of unused pins ....................................................... 18 2. function blocks ............................................................................................................. ............22 2.1 internal units.............................................................................................................. .............................. 22 3. cpu functions................................................................................................................ ................25 4. memory map .................................................................................................................. .................26 5. external bus interface function.....................................................................................28 6. interrupt servicing/exception processing function ..............................................31 7. clock generation function.................................................................................................. 34 8. power save function ........................................................................................................ .......35 9. timer/counter function...................................................................................................... .....37 10. real-time counter function ................................................................................................ .40 11. watchdog timer function................................................................................................... ...41 12. serial interface function................................................................................................. ....42 12.1 3-wire serial i/o (csin)................................................................................................... ......................... 42 12.2 asynchronous serial interface (uart0 and uart1) ........................................................................... 4 4 12.3 i 2 c bus (i 2 c) ( pd703201y, 703204y, 70f3201y, 70f3204y) ................................................................ 45 13. a/d converter.............................................................................................................. .................46 14. d/a converter.............................................................................................................. .................48 15. dma function............................................................................................................... ..................49 16. rom correction function ................................................................................................... ...50 17. reset function............................................................................................................. ................51 18. flash memory ( pd70f3201, 70f3201y, 70f3204, 70f3204y) ............................................52 19. instruction set list...................................................................................................... ............54 19.1 conventions ................................................................................................................ ............................. 54
preliminary product information u15436ej1v0pm 10 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 19.2 instruction set (in alphabetical order) .................................................................................... ..............57 20. electrical specifications (target values) ................................................................. 64 21. package drawings........................................................................................................... .......... 92 appendix development tools .................................................................................................. ... 94
preliminary product information u15436ej1v0pm 11 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 1. pin functions 1.1 port pins (1/3) pin name i/o pull function alternate function p00 nmi p01 intp0/ti2 p02 intp1/ti3 p03 intp2/ti4 p04 intp3/ti5 p05 i/o yes port 0 6-bit i/o port input/output can be specified in 1-bit units. intp4 [p20] [si4] [p21] [so4] [p22] i/o yes port 2 3-bit i/o port input/output can be specified in 1-bit units. n-ch open drain can be specified in 1-bit units (p21, p22 only). [sck4] p30 si1/rxd0 p31 so1/txd0 p32 i/o yes port 3 3-bit i/o port input/output can be specified in 1-bit units. n-ch open drain can be specified in 1-bit units (p31, p32 only). sck1 p40 si0 p41 so0/sda note p42 sck0/scl note p43 intp00/ti0/tclr0 p44 intp01/to0 p45 intp10/ti1/tclr1 p46 i/o yes port 4 7-bit i/o port input/output can be specified in 1-bit units. n-ch open drain can be specified in 1-bit units (p41, p42 only). intp11/to1 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 ani7 p78 ani8 p79 ani9 p710 ani10 p711 ani11 [p712] [ani12] [p713] [ani13] [p714] [ani14] [p715] input no port 7 12-bit input port (v850es/sa2) 16-bit input port (v850es/sa3) [ani15] note applies to the pd703201y, 703204y, 70f3201y, and 70f3204y only. remarks 1. pull: on-chip pull-up resistor 2. pins in brackets ([ ]) are only for the v850es/sa3.
preliminary product information u15436ej1v0pm 12 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (2/3) pin name i/o pull function alternate function p80 ano0 p81 input no port 8 2-bit input port ano1 p90 a0 p91 a1 p92 a2/intp5 p93 a3/intp6 p94 a4/to2 p95 a5/to3 p96 a6/to4 p97 a7/to5 p98 a8/rxd1 p99 a9/txd1 p910 a10/si2 p911 a11/so2 p912 a12/sck2 p913 a13/si3 p914 a14/so3 p915 i/o yes port 9 16-bit i/o port input/output can be specified in 1-bit units. n-ch open drain can be specified in 1-bit units (p911, p912, p914, p915 only). a15/sck3 [pcd1] ? [pcd2] ? [pcd3] i/o no port cd 3-bit i/o port input/output can be specified in 1-bit units. ? pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq [pcm4] ? [pcm5] i/o no 4-bit i/o port (v850es/sa2) 6-bit i/o port (v850es/sa3) input/output can be specified in 1-bit units. ? pcs0 cs0 pcs1 cs1 pcs2 cs2 pcs3 cs3 [pcs4] ? [pcs5] ? [pcs6] ? [pcs7] i/o no port 10 4-bit i/o port (v850es/sa2) 8-bit i/o port (v850es/sa3) input/output can be specified in 1-bit units. ? remarks 1. pull: on-chip pull-up resistor 2. pins in brackets ([ ]) are only for the v850es/sa3.
preliminary product information u15436ej1v0pm 13 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (3/3) pin name i/o pull function alternate function pct0 wr0 pct1 wr1 [pct2] ? [pct3] ? pct4 rd pct5 ? pct6 astb pct7 i/o no port ct 6-bit i/o port (v850es/sa2) 8-bit i/o port (v850es/sa3) input/output can be specified in 1-bit units. ? pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 pdh5 a21 [pdh6] [a22] [pdh7] i/o no port dh 6-bit i/o port (v850es/sa2) 8-bit i/o port (v850es/sa3) input/output can be specified in 1-bit units. [a23] pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5/flmd1 note pdl6 ad6 pdl7 ad7 pdl8 ad8 pdl9 ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 pdl15 i/o no port dl 16-bit i/o port input/output can be specified in 1-bit units. ad15 note applies to the pd70f3201, 70f3201y, 70f3204, and 70f3204y only. remarks 1. pull: on-chip pull-up resistor 2. pins in brackets ([ ]) are only for the v850es/sa3.
preliminary product information u15436ej1v0pm 14 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 1.2 non-port pins (1/4) pin name i/o pull function alternate function a0 p90 a1 p91 a2 p92/intp5 a3 p93/intp6 a4 p94/to2 a5 p95/to3 a6 p96/to4 a7 p97/to5 a8 p98/rxd1 a9 p99/txd1 a10 p910/si2 a11 p911/so2 a12 p912/sck2 a13 p913/si3 a14 p914/so3 a15 output yes address bus for external memory (when using separate bus) p915/sck3 a16 to a21, [a22, a23] output no address bus for external memory pdh0 to pdh5, [pdh6, pdh7] ad0 to ad4 pdl0 to pdl4 ad5 pdl5/flmd1 note ad6 to ad15 i/o no address/data bus for external memory pdl6 to pdl15 ani0 p70 ani1 p71 ani2 p72 ani3 p73 ani4 p74 ani5 p75 ani6 p76 ani7 p77 ani8 p78 ani9 p79 ani10 p710 ani11 p711 [ani12] [p712] [ani13] [p713] [ani14] [p714] [ani15] input no analog voltage input for a/d converter [p715] note applies to the pd70f3201, 70f3201y, 70f3204, and 70f3204y only. remarks 1. pull: on-chip pull-up resistor 2. pins in brackets ([ ]) are only for the v850es/sa3.
preliminary product information u15436ej1v0pm 15 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (2/4) pin name i/o pull function alternate function ano0 p80 ano1 output no analog voltage output for d/a converter p81 astb output no address strobe signal output for external memory pct6 av dd ? ? positive power supply for a/d converter (same potential as v dd )? av ref0 reference voltage input for a/d converter ? av ref1 input ? reference voltage input for d/a converter ? av ss ? ? ground potential for a/d, d/a converters (same potential as v ss )? clkout output no internal system clock output pcm1 cs0 to cs3 output no chip select output pcs0 to pcs3 ev dd ? ? positive power supply for external devices (same potential as v dd ) ? ev ss ? ? ground potential for external devices (same potential as v ss )? flmd0 note 1 ? flmd1 note 1 input no flash programming mode lead-in pins pdl5/ad5 hldak output no bus hold acknowledge output pcm2 hldrq input no bus hold request input pcm3 ic ? ? internally connected (directly connect to v ss ). ( pd703201, 703201y, 703204, and 703204y only) ? intp0 to intp3 p01/ti2 to p04/ti5 intp4 p05 intp5 p92/a2 intp6 input yes external interrupt request input (maskable, analog noise elimination) p93/a3 intp00 p43/ti0/tclr0 intp01 capture trigger input (tm0) p44/to0 intp10 p45/ti1/tclr1 intp11 input yes capture trigger input (tm1) p46/to1 nmi input yes external interrupt input (non-maskable, analog noise elimination) p00 rd output no read strobe signal output for external memory pct4 reset input ? system reset input ? rxd0 serial receive data input (uart0) p30/si1 rxd1 input yes serial receive data input (uart1) p98/a8 sck0 serial clock i/o (csi0) p42/scl note 2 sck1 serial clock i/o (csi1) p32 sck2 serial clock i/o (csi2) p912/a12 sck3 serial clock i/o (csi3) p915/a15 [sck4] i/o yes serial clock i/o (csi4) [p22] scl note 2 i/o yes serial clock i/o (i 2 c) p42/sck0 sda note 2 i/o yes serial transmit/receive data i/o (i 2 c) p41/so0 notes 1. applies to the pd70f3201, 70f3201y, 70f3204, and 70f3204y only. 2. applies to the pd703201y, 703204y, 70f3201y, and 70f3204y only. remarks 1. pull: on-chip pull-up resistor 2. pins in brackets ([ ]) are only for the v850es/sa3.
preliminary product information u15436ej1v0pm 16 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (3/4) pin name i/o pull function alternate function si0 serial receive data input (csi0) p40 si1 serial receive data input (csi1) p30/rxd0 si2 serial receive data input (csi2) p910/a10 si3 serial receive data input (csi3) p913/a13 [si4] input yes serial receive data input (csi4) [p20] so0 serial transmit data output (csi0) p41/sda note so1 serial transmit data output (csi1) p31/txd0 so2 serial transmit data output (csi2) p911/a11 so3 serial transmit data output (csi3) p914/a14 [so4] output yes serial transmit data output (csi4) [p21] tclr0 timer clear input (tm0) p43/intp00/ti0 tclr1 input yes timer clear input (tm1) p45/intp10/ti1 ti0 external event/clock input (tm0) p43/intp00/tclr0 ti1 external event/clock input (tm1) p45/intp10/tclr1 ti2 external event/clock input (tm2) p01/intp0 ti3 external event/clock input (tm3) p02/intp1 ti4 external event/clock input (tm4) p03/intp2 ti5 input yes external event/clock input (tm5) p04/intp3 to0 timer output (tm0) p44/intp01 to1 timer output (tm1) p46/intp11 to2 timer output (tm2) p94/a4 to3 timer output (tm3) p95/a5 to4 timer output (tm4) p96/a6 to5 output yes timer output (tm5) p97/a7 txd0 serial transmit data output (uart0) p31/so1 txd1 output yes serial transmit data output (uart1) p99/a9 v dd ? ? positive power supply pin for internal functions (except for subclock oscillator, rtc, and internal ram) ? v dd bu ? ? positive power supply pin for backup (for subclock oscillator, rtc and internal ram) ? v ss ? ? ground potential for internal functions (except for subclock oscillator, rtc, and internal ram) ? v ss bu ? ? ground potential for backup (for subclock oscillator, rtc and internal ram) ? wait input no external wait input pcm0 wr0 write strobe for external memory (lower 8 bits) pct0 wr1 output no write strobe for external memory (higher 8 bits) pct1 note applies to the pd703201y, 703204y, 70f3201y, and 70f3204y only. remarks 1. pull: on-chip pull-up resistor 2. pins in brackets ([ ]) are only for the v850es/sa3.
preliminary product information u15436ej1v0pm 17 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (4/4) pin name i/o pull function alternate function x1 input ? x2 ? no connecting resonator for main clock ? xt1 input ? xt2 ? no connecting resonator for subclock ? remark pull: on-chip pull-up resistor
preliminary product information u15436ej1v0pm 18 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 1.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are show in table 1-1. for the schematic circuit diagram of each type, refer to figure 1-1. table 1-1. types of pin i/o circuits (1/2) pin alternate function i/o circuit type recommended connection of unused pins p00 nmi p01 to p04 intp0/ti2 to intp3/ti5 p05 intp4 5-w [p20] [si4] 5-w [p21] [so4] 10-e [p22] [sck4] 10-f p30 si1/rxd0 5-w p31 so1/txd0 10-e p32 sck1 10-f p40 si0 5-w p41 so0/sda note 10-f p42 sck0/scl note 10-f p43 intp00/ti0/tclr0 p44 intp01/to0 p45 intp10/ti1/tclr1 p46 intp11/to1 5-w input: independently connect to ev dd or ev ss via a resistor. output: leave open. p70 to p711, [p712 to p715] ani0 to ani15 9 p80, p81 ano0, ano1 34 independently connect to av dd or av ss via a resistor. p90, p91 a0, a1 5-a p92, p93 a2/intp5, a3/intp6 5-w p94 to p97 a4/to2 to a7/to5 5-a p98 a8/rxd1 5-w p99 a9/txd1 5-a p910 a10/si2 5-w p911 a11/so2 10-e p912 a12/sck2 10-f p913 a13/si3 5-w p914 a14/so3 10-e p915 a15/sck3 10-f [pcd1 to pcd3] ? pcm0 wait pcm1 clkout pcm2 hldak 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. note applies to the pd703201y, 703204y, 70f3201y, and 70f3204y only. remark pins in brackets ([ ]) are only for the v850es/sa3.
preliminary product information u15436ej1v0pm 19 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y table 1-1. types of pin i/o circuits (2/2) pin alternate function i/o circuit type recommended connection of unused pins pcm3 hldrq [pcm4] ? [pcm5] ? pcs0 to pcs3 cs0 to cs3 [pcs4 to pcs7] ? pct0, pct1 wr0, wr1 [pct2, pct3] ? pct4 rd pct5 ? pct6 astb pct7 ? pdh0 to pdh5, [pdh6, pdh7] a16 to a21, [a22, a23] pdl0 to pdl4 ad0 to ad4 pdl5 ad5/flmd1 note 1 pdl6 to pdl15 ad6 to ad15 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. av dd ?? ? av ref0 ? ? connect to av ss via a resistor. av ref1 ? ? connect to av ss via a resistor. av ss ?? ? ev dd ?? ? ev ss ?? ? flmd0 note 1 ?? ? ic note 2 ?? ? reset ? 2 ? v dd ?? ? v dd bu ? ? ? v ss ?? ? v ss bu ? ? ? x1 ? ? ? x2 ? ? ? xt1 ? 16 connect to v ss bu via a resistor. xt2 ? 16 leave open. notes 1. applies to the pd70f3201, 70f3201y, 70f3204, and 70f3204y only. 2. applies to the pd703201, 703201y, 703204, and 703204y only. remark pins in brackets ([ ]) are only for the v850es/sa3.
preliminary product information u15436ej1v0pm 20 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y figure 1-1. pin i/o circuits (1/2) type 2 schmitt-triggered input with hysteresis characteristics in data output disable p-ch in/out ev dd n-ch input enable data output disable p-ch in/out ev dd n-ch input enable p-ch ev dd pullup enable data output disable p-ch in/out ev dd n-ch input enable p-ch ev dd pullup enable in comparator + ? av ref0 (threshold voltage) p-ch n-ch input enable type 5 type 5-a type 10-e type 9 type 5-w input enable data output disable p-ch in/out ev dd n-ch p-ch ev dd pullup enable open drain
preliminary product information u15436ej1v0pm 21 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y figure 1-1. pin i/o circuits (2/2) p-ch feedback cut-off xt1 xt2 type 10-f type 34 type 16 in/out analog output voltage p-ch n-ch input enable data output disable open drain p-ch in/out ev dd n-ch p-ch ev dd pullup enable input enable
preliminary product information u15436ej1v0pm 22 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 2. function blocks 2.1 internal units each internal unit of the v850es/sa2 and v850es/sa3 is described below. (1) cpu the cpu uses five-stage pipeline control to enable 1-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as the multiplier (16 bits 16 bits 32 bits) and the barrel shifter (32 bits), helps accelerate processing of complex instructions. (2) bus control unit (bcu) the bcu starts the required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory area and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an internal instruction queue. (3) rom this consists of a 256 kb mask rom or flash memory mapped to the address space 0000000h to 003ffffh. this area can be accessed by the cpu in 1-clock cycle when an instruction is fetched. (4) ram this consists of a 16 kb ram mapped to the address space 3ffb000h to 3ffefffh. this area can be accessed by the cpu in 1-clock cycle. (5) interrupt controller (intc) this controller services hardware interrupt requests (nmi, intp0 to intp6) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiple servicing control can be performed for interrupt sources. (6) clock generator (cg) the clock generator includes two types of oscillators, one for the main clock (f xx ) and one for the subclock (f xt ), generates five types of clocks (f xx , f xx /2, f xx /4, f xx /8, f xx /16, and f xx /32), and supplies one of them as the operating clock for the cpu (f cpu ). the subclock can only be selected as the operation clock of the real-time counter. (7) timer/counter a two-channel 16-bit timer/event counter and a four-channel 8-bit timer/event counter are incorporated, which enables measurement of pulse intervals and frequency as well as programmable pulse output. two channels of the 8-bit timer/event counter can be connected via a cascade connection to enable use as a 16-bit timer.
preliminary product information u15436ej1v0pm 23 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (8) real-time counter (for watch) this counter counts the reference time period (1 second) for watch counting by using the 32.768 khz subclock or the main clock. at the same time, the real-time counter can also be used as an interval timer that uses the main clock as a source clock. this counter includes week, date, hour, minute, and second counters, and is capable of counting up to 4,095 weeks. (9) watchdog timer this timer detects inadvertent program loops, system abnormalities, etc. it can also be used as an interval timer. when used as a watchdog timer, it generates a non-maskable interrupt request (intwdt) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request (intwdtm) after an overflow occurs. (10)serial interface (sio) the v850es/sa2 and v850es/sa3 incorporate three kinds of serial interfaces: asynchronous serial interfaces (uart0 and uart1), clocked serial interfaces (v850e/sa2: csi0 to csi3, v850es/sa3: csi0 to csi4), and an i 2 c bus interface (i 2 c). the v850es/sa2 is capable of using up to 4 channels and the v850es/sa3 is capable of using up to 5 channels simultaneously. among these channels, one channel can be switched between uart and csi, and other one channel can be switched between csi and i 2 c. for uart0 and uart1, data is transferred via the txdo, txd1, rxd0, and rxd1 pins. for csi0 to csi3, data is transferred via the so0 to so3, si0 to si3, and sck0 to sck3 pins. for csi4, data is transferred via the so4, si4, and sck4 pins (v850es/sa3 only). for i 2 c, data is transferred via the sda and scl pins. i 2 c is incorporated in the pd703201y, 703204y, 70f3201y and 70f3204y only. uart includes an on-chip dedicated baud rate generator. (11)a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins for the v850es/sa2 and 16 for the v850es/sa3. conversion is performed using the successive approximation method. (12)d/a converter a two-channel 8-bit resolution d/a converter is incorporated. this d/a converter uses the r string method. (13)dma controller a 4-channel dma controller is incorporated. data is transferred between internal ram, on-chip peripheral i/o, and external memory based on interrupt requests by the on-chip peripheral i/o. (14)rom correction this is a function that replaces a part of the program in the mask rom with a program in the internal ram for execution. four points can be corrected.
preliminary product information u15436ej1v0pm 24 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (15)ports the ports function as both general-purpose ports and control pins, as shown below. port i/o port function control function p0 6-bit i/o nmi, external interrupt, timer input p2 note 3-bit i/o serial interface p3 3-bit i/o serial interface p4 7-bit i/o serial interface, timer i/o, timer trigger p7 12-bit input (v850es/sa2) 16-bit input (v850es/sa3) a/d converter analog input p8 2-bit input d/a converter analog output p9 16-bit i/o external address bus, serial interface, timer output, external interrupt pcd note 3-bit i/o ? pcm 4-bit i/o (v850es/sa2) 6-bit i/o (v850es/sa3) external bus interface pcs 4-bit i/o (v850es/sa2) 8-bit i/o (v850es/sa3) chip select output pct 6-bit i/o (v850es/sa2) 8-bit i/o (v850es/sa3) external bus interface pdh 6-bit i/o (v850es/sa2) 8-bit i/o (v850es/sa3) external address bus pdl 16-bit i/o general- purpose port external address/data bus note v850es/sa3 only
preliminary product information u15436ej1v0pm 25 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 3. cpu functions the cpu of the v850es/sa2 and v850es/sa3 is based on risc architecture and executes most instructions in a 1-clock cycle by using a 5-stage pipeline. the features of the cpu are as follows. { minimum instruction execution time: 59 ns (@ 17 mhz operation with main system clock (f xx )) 74 ns (@ 13.5 mhz operation with main system clock (f xx )) { address space: 64 mb linear ? memory block division function: 2 mb, 2 mb, 4 mb, 8 mb = total four blocks { general-purpose registers: 32 bits 32 { internal 32-bit architecture { 5-stage pipeline control { multiplication/division instructions { saturation operation instructions { 1-clock 32-bit shift instruction { load/store instructions with long/short format { internal memory ? mask rom: 256 kb ( pd703201, 703201y, 703204, 703204y) flash memory: 256 kb ( pd70f3201, 70f3201y, 70f3204, 70f3204y) ? ram: 16 kb { four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1
preliminary product information u15436ej1v0pm 26 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 4. memory map the memory maps of the v850es/sa2 and v850es/sa3 are shown below. { { { { address space program space peripheral i/o area internal ram area reserved area external memory area programmable peripheral i/o area internal rom area (external memory area) data space image 63 image 1 image 0 peripheral i/o area internal ram area reserved area external memory area programmable peripheral i/o area note or reserved area internal rom area (external memory area) 16 mb 64 mb 4 gb 64 mb note the programmable peripheral i/o area in the data space can only be used for image 4n (n = 0 to 15). it cannot be used for other images (reserved area). remark internal rom: 256 kb (0000000h to 003ffffh) internal ram: 16 kb (3ffb000h to 3ffefffh)
preliminary product information u15436ej1v0pm 27 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y { { { { data memory map 3ffffffh 3fec000h 3febfffh 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 01fffffh 0100000h 00fffffh 3ffb000h 3ffafffh 3fff000h 3ffefffh 3ffffffh 0000000h 3fec000h (80 kb) reserved area external memory area note 1 (8 mb) internal rom area note 2 (1 mb) external memory area (1 mb) internal ram area (16 kb) on-chip peripheral area (4 kb) reserved area external memory area (4 mb) external memory area (2 mb) (2 mb) cs0 cs1 cs2 cs3 notes 1. in the v850es/sa2, this area is the 4 mb space of 0800000h to 0bfffffh (0c00000h to 0ffffffh is an image of 0800000h to 0bfffffh). 2. this area is used as an external memory area during data write access.
preliminary product information u15436ej1v0pm 28 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 5. external bus interface function the v850es/sa2 and v850es/sa3 incorporate an external bus interface function that can be used to connect memories, such as rom or ram, and peripheral i/o externally. the external bus interface function has the following features. { separate bus/multiplexed bus output selectable { 8-bit/16-bit data bus sizing function { chip select function for four spaces { wait function ? programmable wait function ? external wait function { idle state function { bus hold function the following pins are used for the external bus interface. table 5-1. list of bus control pins (when multiplexed bus is selected) bus control pin alternate function i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a23 note pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock cs0 to cs3 pcs0 to pcs3 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control note a16 to a21 in the v850es/sa2. table 5-2. list of bus control pins (when separate bus is selected) bus control pin alternate function i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a23 note pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock cs0 to cs3 pcs0 to pcs3 output chip select wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq pcm3 input hldak pcm2 output bus hold control note a16 to a21 in the v850es/sa2.
preliminary product information u15436ej1v0pm 29 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y the number of basic clocks required for accessing each area in the address space is as follows. table 5-3. number of access clocks area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 or 2 3 + n note instruction fetch (branch) 2 1 or 2 3 + n note operand data access 3 1 3 + n note note 2 + n clocks when the separate bus is selected. n is the number of waits. figure 5-1. example of timing in separate bus mode (read write) t1 t2 address address data data wait (input) ad0 to ad15 (i/o) wr0, wr1 (output) rd (output) a0 to a23 (output) clkout (output) t2 t1 remark the broken lines indicates the high-impedance state
preliminary product information u15436ej1v0pm 30 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y figure 5-2. example of timing in multiplexed bus mode (read write) t1 t2 t3 clkout (output) a0 to a23 (output) ad0 to ad15 (i/o) address data address astb (output) rd (output) wait (input) wr0, wr1 (output) t1 t2 t3 address data address remark the broken lines indicate the high-impedance state.
preliminary product information u15436ej1v0pm 31 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 6. interrupt servicing/exception processing function the features of the interrupt servicing/exception processing function are as follows. { interrupt ? non-maskable interrupt: 2 sources ? maskable interrupt pd703201, 70f3201: external 8, internal 30 sources pd703201y, 70f3201y: external 8, internal 31 sources pd703204, 70f3204: external 8, internal 31 sources pd703204y, 70f3204y: external 8, internal 32 sources ? 8-level programmable priority control ? mask specification for the interrupt request according to priority ? mask specification for each maskable interrupt request ? noise elimination, edge detection, and valid edge specification of an external interrupt request { exceptions ? software exception: 32 sources ? exception trap: 2 sources (illegal op code exception, debug trap) table 6-1 shows the interrupt/exception sources.
preliminary product information u15436ej1v0pm 32 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y table 6-1. interrupt source list (1/2) type classifi- cation default priority name trigger g enera- ting unit exception code handler address restored pc interrupt control register reset pin input pin reset interrupt ? reset wdt overflow (wdtres) wdt 0000h 00000000h undefined ? ? nmi nmi pin valid edge input ? 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt wdt overflow wdt 0020h 00000020h nextpc ? ? trap0n note trap instruction ? 004nh note 00000040h nextpc ? software exception exception ? trap1n note trap instruction ? 005nh note 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal op code/ dbtrap instruction ? 0060h 00000060h nextpc ? 0 intwdtm internal timer overflow wdt 0080h 00000080h nextpc wdtic 1 intp0 intp0 pin valid edge input pin 0090h 00000090h nextpc pic0 2intp1 intp1 pin valid edge input pin 00a0h 000000a0h nextpc pic1 3intp2 intp2 pin valid edge input pin 00b0h 000000b0h nextpc pic2 4intp3 intp3 pin valid edge input pin 00c0h 000000c0h nextpc pic3 5 intp4 intp4 pin valid edge input pin 00d0h 000000d0h nextpc pic4 6 intp5 intp5 pin valid edge input pin 00e0h 000000e0h nextpc pic5 7 intp6 intp6 pin valid edge input pin 00f0h 000000f0h nextpc pic6 8 intrtc rtc interrupt rtc 0100h 00000100h nextpc rtcic 9 intcc00 cc00 capture trigger input/match between tm0 and cc00 tm0 0110h 00000110h nextpc ccic00 10 intcc01 cc01 capture trigger input/match between tm0 and cc01 tm0 0120h 00000120h nextpc ccic01 11 intovf0 tm0 overflow tm0 0130h 00000130h nextpc ovfic0 12 intcc10 cc10 capture trigger input/match between tm1 and cc10 tm1 0140h 00000140h nextpc ccic10 13 intcc11 cc11 capture trigger input/match between tm1 and cc11 tm1 0150h 00000150h nextpc ccic11 14 intovf1 tm1 overflow tm1 0160h 00000160h nextpc ovfic1 15 inttm2 match between tm2 and cr2/tm2 overflow tm2 0170h 00000170h nextpc tmic2 maskable interrupt 16 inttm3 match between tm3 and cr3/tm3 overflow tm3 0180h 00000180h nextpc tmic3 note n: value of 0 to fh
preliminary product information u15436ej1v0pm 33 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y table 6-1. interrupt source list (2/2) type classifi- cation default priority name trigger g enera- ting unit exception code handler address restored pc interrupt control register 17 inttm4 match between tm4 and cr4/tm4 overflow tm4 0190h 00000190h nextpc tmic4 18 inttm5 match between tm5 and cr5/tm5 overflow tm5 01a0h 000001a0h nextpc tmic5 19 intcsi0 csi0 transfer end csi0 01b0h 000001b0h nextpc csiic0 20 intiic note 1 i 2 c transfer end i 2 c 01c0h 000001c0h nextpc iicic0 21 intcsi1 csi1 transfer end csi1 01d0h 000001d0h nextpc csiic1 22 intsre0 uart0 receive error uart0 01e0h 000001e0h nextpc sreic0 23 intsr0 uart0 receive end uart0 01f0h 000001f0h nextpc sric0 24 intst0 uart0 transfer end uart0 0200h 00000200h nextpc stic0 25 intcsi2 csi2 transfer end csi2 0210h 00000210h nextpc csiic2 26 intsre1 uart1 receive error uart1 0220h 00000220h nextpc sreic1 27 intsr1 uart1 receive end uart1 0230h 00000230h nextpc sric1 28 intst1 uart1 transmit end uart1 0240h 00000240h nextpc stic1 29 intcsi3 csi3 transfer end csi3 0250h 00000250h nextpc csiic3 30 intcsi4 note 2 csi4 transfer end csi4 0260h 00000260h nextpc csiic4 31 intad a/d conversion end adc 0270h 00000270h nextpc adic 32 intdma0 dma0 transfer end dma 0280h 00000280h nextpc dmaic0 33 intdma1 dma1 transfer end dma 0290h 00000290h nextpc dmaic1 34 intdma2 dma2 transfer end dma 02a0h 000002a0h nextpc dmaic2 35 intdma3 dma3 transfer end dma 02b0h 000002b0h nextpc dmaic3 36 introv rtc overflow rtc 02c0h 000002c0h nextpc rovic maskable interrupt 37 intbrg brg match brg 02d0h 000002d0h nextpc brgic note 1. valid for the pd703201y, 70f3201y, 703204y and 70f3204y only. 2. valid for the v850e/sa3 only. remarks 1. default priority: priority that applies when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the pc saved to eipc or fepc when interrupt servicing/exception processing is started. however, the value of the restored pc saved when an interrupt is acknowledged during division instruction (div, divh, divu, divhu) execution is the value of the pc of the current instruction (div, divh, divu, divhu). nextpc: the value of the pc to be processed after an interrupt/exception. 2. the execution address of the illegal instruction when an illegal op code exception occurs is calculated with (restored pc ? 4).
preliminary product information u15436ej1v0pm 34 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 7. clock generation function the clock generation function has the following features. { main clock oscillator ? 2 to 17 mhz (@ v dd = 2.3 to 2.7 v operation) ? 2 to 13.5 mhz (@ v dd = 2.2 to 2.7 v operation) { subclock oscillator ? 32.768 khz (@ v dd = 2.2 to 2.7 v operation) { internal system clock generation ? 6 levels (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32) { peripheral clock generation { clock output function the following figure shows the configuration of the clock generation function. frc bit mfrc bit ck2 to ck0 bits stop mode subclock oscillator port cm wdt clock control prescaler 1 prescaler 2 idle control halt control halt mode cpu clock a/d converter rtc clock peripheral clock wdt clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control xt1 xt2 clkout x1 x2 idle mode f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /512 f x /2 6 to f x /2 9 f xt f xt f x f xx f xw selector remark f x, f xx : main clock frequency f xt : subclock frequency f cpu : cpu clock frequency f clk : internal system clock frequency f xw : watchdog timer clock frequency
preliminary product information u15436ej1v0pm 35 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 8. power save function the v850es/sa2 and v850es/sa3 have the following power save functions to realize an effective low-power- consuming system. { halt mode: only the clock of the cpu is stopped in this mode. { idle mode: all operations on the chip other than oscillator operation are stopped in this mode. { stop mode: all operations on the chip other than subclock oscillator operation are stopped in this mode. { backup mode: the power supply other than for the subclock oscillator, real-time counter, and internal ram can be disconnected. the following table shows the operating states of the on-chip peripheral functions in each mode. parameter halt mode idle mode stop mode backup mode v dd , ev dd , av dd power supplied power off possible v dd bu power supplied cpu operation stopped on-chip peripheral function operation enabled stopped main clock oscillator operation enabled stopped subclock oscillator operation enabled real-time counter function, ram retention enabled release condition ? non-maskable interrupt request ? unmasked maskable interrupt request ? reset pin input reset pin input after power is supplied
preliminary product information u15436ej1v0pm 36 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y ? ? ? ? backup mode overview the v850es/sa2 and v850es/sa3 are put in backup mode by stopping supplying power other than the backup power supply (v dd bu) in stop mode. the backup power supply supplies power only to the subclock oscillator, real-time counter, and internal ram, as shown in the figure below. other on-chip functions including the cpu cannot operate since the power supply is stopped. power supply for backup power supply for operation connect to v ss in backup mode backup power supply status flag (bpsf) ram real-time counter subclock oscillator main clock oscillator peripheral function rom cpu i/o function a/d converter d/a converter v dd bu v dd av dd ev dd v ss bu v ss av ss ev ss in backup mode, subclock oscillator operation, real-time counter count operation, and internal ram data retention are enabled. if the voltage is lower than the data retention voltage in backup mode, a backup power supply status flag (bpsf) is set and that internal ram retention data can be detected as invalid. when this flag is set, the real-time counter and the ram should be initialized at reset start. bpsf clear bpsf confirmed (set initialization) bpsf cleared stop execution normal operation backup mode oscillation stabilization normal operation (v dd bu is lower than data retention voltage) stop mode reset mode reset mode backup power supply status flag (bpsf) cpu status v dd bu v dd , ev dd , av dd reset (input)
preliminary product information u15436ej1v0pm 37 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 9. timer/counter function the timer/counter function has the following features. { 16-bit timer/counter (tm0, tm1) ? capture/compare common registers: 2 for each ? interrupt request sources ? capture/match interrupt requests: 2 sources for each ? overflow interrupt requests: 1 source for each ? timer/counter count clock sources: 2 types (selection of external pulse input or internal system clock division) ? either free-running mode or overflow stop mode can be selected as the operation mode when the timer/counter overflows ? timer/counter can be cleared by a match of the timer/counter and a compare register ? external pulse outputs: 1 for each { 8-bit timers (tm2 to tm5) ? stand-alone mode (mode in which a single timer is used) ? interval timer ? external event counter ? square-wave output ? pwm output ? cascade connection mode (mode in which two timers are used connected in cascade: 16-bit resolution) ? 16-bit resolution interval timer ? 16-bit resolution external event counter ? 16-bit resolution square-wave output

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r note 4 q sq tmn (16 bits) note 3 note 3 note 3 ccn0 ccn1 intovn intccn0 intpn1 note 1 tclrn/tin/intpn0 intpn0 tclrn tin intccn1 ton note 1 clear & start f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx selector selector note 2 note 2
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preliminary product information u15436ej1v0pm 39 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (2) tm2 to tm5 ovf clear match mask circuit selector selector selector tin count clock note 3 selector internal bus timer mode control register n (tmcn) timer clock select register n (tcln) invert level internal bus tcln2 tcln1 tcln0 tcen tmcn6 tmcn4 lvsn lvrn tmcn1 toen ton inttmn s r q inv s r q 8-bit counter n (tmn) 8-bit compare register n (crn) note the count clock is set by the tcln register. ? when n = 2, 3 ? when n = 4, 5 f xx /4 f xx /4 f xx /8 f xx /8 f xx /16 f xx /16 f xx /32 f xx /32 f xx /128 f xx /128 f xx /512 f xx /256 remarks 1. ? ] ? is a signal that can be directly connected to a port. 2. n = 2 to 5
preliminary product information u15436ej1v0pm 40 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 10. real-time counter function the real-time counter function has the following features. { includes counters of weeks, days, hours, minutes, and seconds, and can count up to 4,095 weeks. { counters of weeks, days, hours, minutes, and seconds can be read during operation and while operation is stopped. { week counter overflow interrupt request occurrence (introv) { interval interrupt request occurrence (intrtc) at a fixed interval (can be selected from the following) 0.015625 seconds, 0.03125 seconds, 0.0625 seconds, 0.125 seconds, 0.25 seconds, 0.5 seconds, 1 second, 1 minute, 1 hour, 1 day { when subclock (f xt ) is selected, operable only with power supply to v dd bu. the following figure shows the configuration of the real-time counter function. count enable/ disable circuit subcounter (15 bits) second counter (6 bits) internal bus second counter write buffer minute counter write buffer hour counter write buffer day counter write buffer week counter write buffer minute counter (6 bits) hour counter (5 bits) day counter (3 bits) week counter (12 bits) introv intrtc 1 second 0.015625 seconds/0.03125 seconds/0.0625 seconds/0.125 seconds/ 0.25 seconds/0.5 seconds 1 minute 1 hour 1 day count clock = 32.768 khz f xt f x /2 6 to f x /2 9 selector selector remark f x : main clock frequency f xt : subclock frequency
preliminary product information u15436ej1v0pm 41 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 11. watchdog timer function the watchdog timer has the following functions. { watchdog timer { interval timer { timer for oscillation stabilization the following figure shows the configuration of the watchdog timer function. oscmd 13-bit divider run osts0 to osts2, wdcs0 to wdcs2 wdtm3, wdtm4 clear clear 8-bit counter output control f xw f xw /2 13 f xw /2 12 f xw /2 11 f xw /2 10 f xw /2 9 f xw /2 8 f xw /2 7 f xw /2 6 f xw /2 5 ovf intwdtm intwdt wdtres ostovf selector remarks 1. wdtres: reset signal triggered by wdt overflow ostovf: overflow signal for oscillation stabilization oscmd: timer mode signal for oscillation stabilization f xw : watchdog timer clock frequency 2 . during counting of oscillation stabilization time: f xw = f x /2 other than above: f xw = f xx /2
preliminary product information u15436ej1v0pm 42 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 12. serial interface function the v850es/sa2 and v850es/sa3 include the following three types of serial interfaces. type v850es/sa2 v850es/sa3 3-wire serial i/o 4 channels (csi0 to csi3) 5 channels (csi0 to csi4) asynchronous serial interface 2 channels (uart0, uart1) i 2 c bus note 1 channel (i 2 c) note note available only in the pd703201y, 703204y, 70f3201y, and 70f3204y. some functions are used alternately as follows. ? csi0/i 2 c ? csi1/uart0 ? csi2 ? uart1 ? csi3 ? csi4 (v850es/sa3 only) 12.1 3-wire serial i/o (csin) remark in this section, the value of n is as follows. n = 0 to 3 (v850es/sa2) n = 0 to 4 (v850es/sa3) the 3-wire serial i/o (csin) transfers data using following three lines. ? sckn (serial clock) ? son (serial data output) ? sin (serial data input) the 3-wire serial i/o (csin) has the following features. { transfer data length: fixed to 8 bits { transfer data msb/lsb first can be switched { transfer clock can be selected from eight clocks (seven master clocks, one slave clock) { transmit/receive mode or receive-only mode can be specified { on-chip 8-bit transmit buffer { transfer data transmit/receive timing with respect to the transfer clock can be changed
preliminary product information u15436ej1v0pm 43 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y the following figure shows the configuration of the 3-wire serial i/o (csin). cksn0 to cksn2 intcsin csotn son transfer clock controller transfer mode controller transfer data controller transmit buffer (sotbn) selector son latch sin sckn shift register (sion) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 tofm csien, trmdn, dirn, ckpn, dapn selector remarks 1. when n = 0: m = 2 when n = 1: m = 3 when n = 2: m = 4 when n = 3: m = 5 when n = 4: m = 5 (v850es/sa3 only) 2. f xx : main clock frequency
preliminary product information u15436ej1v0pm 44 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 12.2 asynchronous serial interface (uart0 and uart1) the asynchronous serial interface (uart0 and uart1) has the following features. { two modes ? operation stop mode (used when serial transfers are not performed to enable a reduction in power consumption) ? asynchronous serial interface mode { full-duplex transmission { 2-pin configuration ? txd0 and txd1: transmit data output pins ? rxd0 and rxd1: receive data input pins { 3 types of interrupt sources ? receive error interrupt (intsre0 and intsre1) ? receive end interrupt (intsr0 and intsr1) ? transmit end interrupt (intst0 and intst1) { character length: 7 bits/8 bits { parity function: odd, even, 0, none { transmission stop bit: 1 bit/2 bits { on-chip baud rate generator the following figure shows the configuration of the asynchronous serial interface (uart0 and uart1). parity framing overrun internal bus asynchronous serial interface mode register n (asimn) receive buffer (rxbn) receive shift register reception control parity check transmit buffer (txbn) transmit shift register addition of transmission control parity brgn intsren intsrn intstn rxdn txdn remark n = 0, 1
preliminary product information u15436ej1v0pm 45 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 12.3 i 2 c bus (i 2 c) ( pd703201y, 703204y, 70f3201y, 70f3204y) the i 2 c bus has the following features. { two modes ? operation stop mode (used when serial transfers are not performed to enable a reduction in power consumption) ? i 2 c bus mode (supporting multi masters) the following figure shows the configuration of the i 2 c bus internal bus iic status register 0 (iics) iic control register (iicc) slave address register (sva) noise eliminator noise eliminator match signal i ic shift register (iic) so latch iice d q set clear cl1, cl0 sda scl n-ch open drain output n-ch open drain output data hold time correction circuit ack detector wake up controller ack detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic f xx tm4 output cld iic clock select register (iiccl) iic function expansion register (iicx) internal bus lrel wrel spie wtim acke stt spt msts ald exc coi trc ackd std spd start condition detector dad smc dfc cl1 cl0 clx remark f xx : main clock frequency
preliminary product information u15436ej1v0pm 46 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 13. a/d converter the a/d converter has the following features. { 10-bit resolution { 12 channels (v850es/sa2) 16 channels (v850es/sa3) { successive comparison approximation method { power fail detection function available { operation voltage: av dd = av ref0 = 2.2 to 2.7 v { analog input voltage: av ss to av ref0 { conversion rate: 9.5 to 1.50 s the following figure shows the configuration of the a/d converter. comparator av ref0 av dd av ss intad analog input side c array reference side c array controller successive approximation register (sar) a/d conversion result register (adcr) ads0 to ads3 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 ani12 note ani13 note ani14 note ani15 note selector note v850es/sa3 only
preliminary product information u15436ej1v0pm 47 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y the following figure shows the configuration of the power fail detection function. a/d converter comparator power-fail comparison threshold value register (pft) ads0 to ads3 pfcm pfen intad ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 ani12 note ani13 note ani14 note ani15 note selector selector note v850es/sa3 only
preliminary product information u15436ej1v0pm 48 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 14. d/a converter the d/a converter has the following features. { 8-bit resolution 2 channels (dac0, dac1) { r string method { conversion time: 20 s max. (av ref1 = 2.2 to 2.7 v) { analog output voltage: av ref1 m/256 (m = 0 to 255; value set in the dacsn register) { operation mode: normal mode/real-time output mode remark n = 0, 1 the following figure shows the configuration of the d/a converter. dacs0 r string resistor r string resistor dacs1 ano0 ano1 dace0 dace1 dacs0 write damd0 inttm2 dacs1 write damd1 inttm3 av ref1 av ss
preliminary product information u15436ej1v0pm 49 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 15. dma function the dma function has the following features. { transfer unit: 8 bits/16 bits { maximum transfer count: 65,536 (2 16 ) times { transfer type: 2-cycle transfer { transfer mode: single transfer { transfer request: request via interrupt from on-chip peripheral i/o or external pins, request via software trigger { transfer object: on-chip peripheral i/o, internal ram, external memory the relationship between the transfer type and transfer object is shown below ( : transfer enabled, : transfer disabled). transfer destination transfer source on-chip peripheral i/o internal ram external memory on-chip peripheral i/o ?? internal ram ? external memory ?? the following figure shows the configuration of the dma function. v850es core cpu bcu irif data control block address control block count control block channel control block internal ram on-chip peripheral i/o on-chip peripheral i/o bus dsanh/ dsanl ddanh/ ddanl dbcn dchcn dadcn external i/o external bus external ram external rom intdman dmarqn dmactvn dmac remark n = 0 to 3
preliminary product information u15436ej1v0pm 50 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 16. rom correction function the rom correction function is a function that replaces part of a program in the mask rom with a program in the internal ram for execution. first, the address where the program replacement should start (correction address) is set in the correction address register (coradn). when the cpu reads the instruction of the address set in coradn, the instruction is replaced with the dbtrap instruction and the program jumps to 00000060h. a value that is the address saved in the dbpc minus 2 (address to which rom correction generated) is compared with the address set in coradn, and the program jumps to the correction program on the corresponding ram. after executing the correction program, a restore address is set in the dbpc, the dbret instruction is executed, and then execution is restored to the normal program. up to four correction addresses can be specified in coradn. remark n = 3 the following figure shows the configuration of rom correction. instruction address bus correction control register (corenn bit) dbtrap instruction generation block rom (1 mb space) correction address register (coradn) comparator instruction replacement block instruction data bus remark n = 0 to 3
preliminary product information u15436ej1v0pm 51 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 17. reset function when a low-level signal is input to the reset pin or the watchdog timer overflows (wdtres), a system reset is applied and the various on-chip hardware devices are reset to their initial states. when the reset pin goes from low level to high level, or when the wdtres signal is automatically canceled, the reset state is released. when reset is released via reset pin input, the cpu starts execution of the program after securing the oscillation stabilization time (osts register reset value: 2 19 /f xx ). when reset is released by the wdtres signal, the main clock oscillator does not stop and oscillation stabilization time is not inserted. the following figure shows the configuration of the reset function. reset count clock reset controller watchdog timer stop overflow reset signal interrupt function
preliminary product information u15436ej1v0pm 52 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 18. flash memory ( pd70f3201, 70f3201y, 70f3204, 70f3204y) the pd70f3201 and 70f3201y, and 70f3204 and 70f3204y are the flash memory versions of the v850es/sa2 and v850es/sa3, respectively, and incorporate 256 kb of flash memory. writing to flash memory can be performed while the device is mounted on the target system (on board). writing is performed using a dedicated flash programmer connected to the target system or to a writing adapter. the flash memory has the following features. { flash memory: 256 kb (4 kb 4 blocks, 60 kb 4 blocks) { erasure/writing possible using single power supply (v dd = 2.2 to 2.7 v) { erasure unit ? overall area batch erasure (256 kb) ? block units erasure (4 kb/block, 60 kb/block) { erasure/writing method ? serial mode (using csi0 or uart0) ? self-programming mode
preliminary product information u15436ej1v0pm 53 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y an overview of flash memory programming is shown below. { pins used in programming ? power supply pins (v dd , ev dd , av dd , v ss , ev ss , av ss , v dd bu, v ss bu) ? mode pins (flmd0, flmd1) ? clock supply pins (x1, x2) ? serial communication pins (sck0, so0, si0 or rxd0, txd0) ? reset pin { programming timing the following figure shows the programming timing (overview) when using uart. v dd v dd reset (input) flmd1 (input) flmd0 (input) rxd0 (input) txd0 (output) 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v (uart mode only) power on oscillation stabilization communication mode selection flash control command communication (erasure, writing, etc.) reset release
preliminary product information u15436ej1v0pm 54 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 19. instruction set list 19.1 conventions (1) register symbols used to describe operands register symbol explanation reg1 general-purpose register: used as source register. reg2 general-purpose register: used mainly as destination register. also used as source register in some instructions. reg3 general-purpose register: used mainly to store the remainder of division results and the higher 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the condition code sp stack pointer (r3) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of the code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates the higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of the bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list s 1-bit data that specifies a system register in the register list
preliminary product information u15436ej1v0pm 55 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (3) register symbols used in operation register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) half-word halfword (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols used in an execution clock register symbol explanation i if executing another instruction immediately after executing the first instruction (issue). r if repeating execution of the same instruction immediately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately after the execution (latency).
preliminary product information u15436ej1v0pm 56 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition expression explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z/e 0 0 1 0 z = 1 zero equal nz/ne 1 0 1 0 z = 0 not zero not equal nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) n 0 1 0 0 s = 1 negative p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed
preliminary product information u15436ej1v0pm 57 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 19.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation irlcyovszsat reg1,reg2 rrrrr001110rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 rrrrr110000rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 rrrrr001010rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 rrrrr110110rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 0 when conditions are satisfied 2 note 2 2 note 2 2 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 11 1 bsh reg2,reg3 rrrrr11111100000 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 111 0 bsw reg2,reg3 rrrrr11111100000 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 111 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,half-word)) 444 bit#3, disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] rrrrr111111rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 111 cmov cccc,reg1,reg2,reg3 rrrrr111111rrrr wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 111 reg1,reg2 rrrrr001111rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 rrrrr010011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 333rrrrr dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 333rrrrr
preliminary product information u15436ej1v0pm 58 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (2/6) execution clock flags mnemonic operand opcode operation irlcyovszsat dbtrap 1111100001000000 dbpc pc+2 (restored pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 333 di 0000011111100000 0000000101100000 psw.id 1111 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0000011001iiiiil lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) r[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 rrrrr111111rrrrr wwwww01011000000 gr[reg2] gr[reg2}gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 rrrrr000010rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 rrrrr111111rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 rrrrr111111rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 rrrrr111111rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0111 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 rrrrr11111100000 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 rrrrr11110dddddd ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 222 jmp [reg1] 00000000011rrrrr pc gr[reg1] 3 3 3 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 2 2 2 ld.b disp16[reg1],reg2 rrrrr111000rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 11 note 11 ld.bu disp16[reg1],reg2 rrrrr11110brrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 11 note 11
preliminary product information u15436ej1v0pm 59 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (3/6) execution clock flags mnemonic operand opcode operation irlcyovszsat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,half- word)) 11 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 rrrrr111111rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-exend(disp16) gr[reg2] zero-extend(load-memory(adr,half-word) 11 note 11 ld.w disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-exend(disp16) gr[reg2] load-memory(adr,word) 11 note 11 reg1,reg2 rrrrr000000rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 rrrrr110001rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 rrrrr110010rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 )111 reg1,reg2,reg3 rrrrr111111rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] 1 4 5 mul imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 4 5 reg1,reg2 rrrrr000111rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 112 mulh imm5,reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 rrrrr110111rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 rrrrr111111rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] 1 4 5 mulu imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 4 5 nop 000 00 000 00 00 00 00 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 rrrrr000001rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] rrrrr111111rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3
preliminary product information u15436ej1v0pm 60 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (4/6) execution clock flags mnemonic operand opcode operation irlcyovszsat or reg1,reg2 rrrrr001000rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 rrrrr110100rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 14 0000011110iiiiil lllllllllllff011 imm16/imm32 note 15 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) ep sp/imm n+2 note 4 note 16 n+2 note 4 note 16 n+2 note 4 note 16 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 333 rrrrr reg1,reg2 rrrrr111111rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 111 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 111 0 sasf cccc,reg2 r r r r r 1 1 1 1 1 1 0 c c c c 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 111 reg1,reg2 rrrrr000110rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 rrrrr000101rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 rrrrr110011rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 rrrrr000100rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 r r r r r 1 1 1 1 1 1 0 c c c c 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 111 bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] rrrrr111111rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3
preliminary product information u15436ej1v0pm 61 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (5/6) execution clock flags mnemonic operand opcode operation irlcyovszsat reg1,reg2 rrrrr111111rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 111 0 reg1,reg2 rrrrr111111rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 111 0 sld.b disp7[ep],reg2 rrrrr0110ddddddd adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 11 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 17 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 11 note 9 sld.h disp8[ep],reg2 rrrrr1000ddddddd note 18 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,half- word)) 11 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 17, 19 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,half- word)) 11 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 20 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 11 note 9 sst.b reg2,disp7[ep] rrrrr0111ddddddd adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 111 sst.h reg2,disp8[ep] rrrrr1001ddddddd note 18 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],half-word) 111 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 20 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 111 st.b reg2,disp16[reg1] rrrrr111010rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 111 st.h reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], half-word) 111 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 111 stsr regid,reg2 rrrrr111111rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1 sub reg1,reg2 rrrrr001101rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 rrrrr001100rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,half-word))) logically shift left by 1 555
preliminary product information u15436ej1v0pm 62 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (6/6) execution clock flags mnemonic operand opcode operation irlcyovszsat sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 111 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 111 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (restored pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh) 00000050h (when vector is 10h to 1fh) 333 tst reg1,reg2 rrrrr001011rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] rrrrr111111rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 rrrrr001001rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 rrrrr110101rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 3 clocks if the final instruction includes the psw write access. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list x load registers. (according to the number of wait states. also, if there are no wait states, n is the number of list x registers.) 5. rrrrr: other than 00000. 6. the lower halfword data only is valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait states (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait states (2 if there are no wait states). 12. in this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regid specification rrrrr = reg2 specification 13. i i i i i : lower 5 bits of imm9. i i i i : lower 4 bits of imm9. 14. sp/imm: specified by bits 19 and 20 of the sub-opcode.
preliminary product information u15436ej1v0pm 63 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y notes 15. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 16. if imm = imm32, n + 3 clocks. 17. r r r r r : other than 00000. 18. ddddddd: higher 7 bits of disp8. 19. dddd: higher 4 bits of disp5. 20. dddddd: higher 6 bits of disp8.
preliminary product information u15436ej1v0pm 64 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 20. electrical specifications (target values) absolute maximum ratings (t a = 25c, v ss = 0 v) parameter symbol conditions ratings unit v dd ?0.5 to +3.6 v av dd ?0.5 to +3.6 v ev dd ?0.5 to +3.6 v v dd bu ?0.5 to +3.6 v av ss ?0.5 to +0.5 v ev ss ?0.5 to +0.5 v supply voltage v ss bu ?0.5 to +0.5 v input voltage v i other than x1, xt1, and port 7 ?0.5 to ev dd + 0.3 note v v k x1, v dd = 2.2 to 2.7 v ?0.5 to v dd + 0.3 note v clock input voltage v kt xt1, v dd bu = 2.2 to 2.7 v ?0.5 to v dd bu + 0.3 note v analog input voltage v ian port 7 ?0.5 to av dd + 0.3 note v analog reference voltage av ref av ref0 , av ref1 ?0.5 to av dd + 0.3 note v per pin 4 ma output current, low i ol total for all pins 100 ma per pin ?4 ma output current, high i oh total for all pins ?100 ma output voltage v o v dd = 2.5 v 0.2 v ?0.5 to v dd + 0.3 v v normal operation mode ?40 to +85 c operating ambient temperature t a flash programming mode t.b.d. c pd703201, 703201y, 703204, 703204y ?65 to +150 c storage temperature t stg pd70f3201, 70f3201y, 70f3204, 70f3204y t.b.d. c note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-collector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation.
preliminary product information u15436ej1v0pm 65 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y capacitance (t a = 25c, v dd = av dd = ev dd = v dd bu = v ss = av ss = ev ss = v ss bu = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 10 pf i/o capacitance c io 10 pf output capacitance c o f x = 1 mhz unmeasured pins returned to 0 v 10 pf operating conditions (v dd = av dd = ev dd = v dd bu) parameter symbol conditions min. typ. max. unit @ v dd = 2.3 to 2.7 v, operation with main clock 0.0625 17 mhz internal system clock frequency f clk @ v dd = 2.2 to 2.7 v, operation with main clock 0.0625 13.5 mhz
preliminary product information u15436ej1v0pm 66 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y recommended oscillator (1) main clock oscillator (t a = ?40 to +85c) (a) connection of ceramic resonator or crystal resonator x1 x2 parameter symbol conditions min. typ. max. unit v dd = 2.3 to 2.7 v 2 17 mhz oscillation frequency f x (f xx ) v dd = 2.2 to 2.7 v 2 13.5 mhz upon reset release 2 19 /f x s oscillation stabilization time upon stop mode release note s note the typ. value differs depending on the setting of the oscillation stabilization time select register (osts). caution ensure that the duty of the oscillation waveform is between 45% and 55%. remarks 1. connect the oscillator as close as possible to the x1 and x2 pins. 2. do not route the wiring near broken lines. 3. for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (b) external clock input x1 x2 high-speed cmos inverter external clock open cautions 1. connect the high-speed cmos inverter as close as possible to the x1 pin. 2. sufficiently evaluate the matching between the v850es/sa2, v850es/sa3 and the high- speed cmos inverter.
preliminary product information u15436ej1v0pm 67 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (2) subclock oscillator (t a = ?40 to +85c) (a) connection of crystal resonator xt1 xt2 parameter symbol conditions min. typ. max. unit oscillation frequency f xt 32 32.768 35 khz oscillation stabilization time 10 s caution ensure that the duty of the oscillation waveform is between 45% and 55%. remarks 1. connect the oscillator as close as possible to the xt1 and xt2 pins. 2. do not route the wiring near broken lines. 3. for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
preliminary product information u15436ej1v0pm 68 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y dc characteristics (t a = ?40 to +85c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 note 1 0.7ev dd ev dd v v ih2 note 2 t.b.d. ev dd v v ih3 note 3 0.7av dd av dd v v ih4 x1 0.8v dd v dd v input voltage, high v ih5 xt1, xt2 0.8v dd bu v dd bu v v il1 note 1 ev ss 0.3ev dd v v il2 note 2 ev ss t.b.d. v v il3 note 3 av ss 0.3av dd v v il4 x1 v ss 0.2v dd v input voltage, low v il5 xt1, xt2 v ss bu 0.2v dd bu v v oh1 note 4 i oh = ? 1 ma 0.8ev dd v output voltage, high v oh2 note 5 i oh = ? 3 ma 0.8ev dd v v ol1 note 4 (except pins p40 and p42) i ol = 1.6 ma 0.4 v v ol2 p40, p42 i ol = 3 ma 0.4 v output voltage, low v ol3 note 5 i ol = 1.6 ma 0.4 v input leakage current, high i lih v in = v dd = ev dd = v dd bu 5 a input leakage current, low i lil v in = 0 v ? 5 a output leakage current, high i loh v o = v dd = ev dd = v dd bu 5 a output leakage current, low i lol v o = 0 v ? 5 a notes 1. p21, p31, p90, p91, p94 to p97, p99, p911, p914, pcd1 to pcd3, pcm0 to pcm5, pcs0 to pcs7, pct0 to pct7, pdh0 to pdh7, pdl0 to pdl15 (and their alternate-function pins) 2. reset, p00 to p05, p20, p22, p30, p32, p40 to p46, p92, p93, p98, p910, p912, p913, p915 (and their alternate-function pins) 3. p70 to p715, p80, p81 (and their alternate-function pins) 4. p00 to p05, p20 to p22, p30 to p32, p40 to p46, pcd1 to pcd3, pcm4 to pcm5, pcs4 to pcs7, pct2, pct3, pct5, pct7 (and their alternate-function pins) 5. p90 to p915, pcm0 to pcm3, pcs0 to pcs3, pct0, pct1, pct4, pct6, pdh0 to pdh7, pdl0 to pdl15 (and their alternate-function pins)
preliminary product information u15436ej1v0pm 69 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (t a = ?40 to +85c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v) (2/2) parameter symbol conditions min. typ. max. unit v dd = 2.3 to 2.7 v, f xx = f clk = 17 mhz t.b.d. t.b.d. ma i dd1 normal operation all peripheral functions operating f xx = f clk = 13.5 mhz t.b.d. t.b.d. ma v dd = 2.3 to 2.7 v, f xx = f clk = 17 mhz t.b.d. t.b.d. ma i dd2 halt mode all peripheral functions operating f xx = f clk = 13.5 mhz t.b.d. t.b.d. ma v dd = 2.3 to 2.7 v, f xx = f clk = 17 mhz t.b.d. t.b.d. ma i dd3 idle mode rtc operating f xx = f clk = 13.5 mhz t.b.d. t.b.d. ma subclock oscillator, rtc operating t.b.d. t.b.d. a i dd4 stop mode subclock oscillator stopped (xt1 = v ss ) t.b.d. t.b.d. a f xt = 32.768 khz, rtc operating t.b.d. t.b.d. a supply current i dd5 backup mode subclock oscillation stopped (xt1 = v ss ) t.b.d. t.b.d. a pull-up resistance r l v in = 0 v 10 30 100 k ?
preliminary product information u15436ej1v0pm 70 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y data retention characteristics (1) in stop mode (t a = ?40 to +85c, v ss = av ss = ev ss = v ss bu = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr1 stop mode 1.8 2.7 v data retention current i dddr1 v dd = av dd = ev dd = v dd bu = v dddr1 t.b.d. t.b.d. a supply voltage rise time t rvd1 200 s supply voltage fall time t fvd1 200 s supply voltage hold time (from stop mode setting) t hvd1 0ms stop release signal input time t drel1 0ms data retention high-level input voltage v ihdr1 all input ports v ihn v dddr1 v data retention low-level input voltage v ildr1 all input ports 0 v iln v remark n = 1 to 5 v dd setting stop mode t hvd1 t fvd1 reset (input) nmi, intp0 to intp6 (input) nmi, intp0 to intp6 (input) (when stop mode is released at rising edge) t rvd1 t drel1 v dddr1 v ihdr1 v ildr1 v ihdr1 caution shifting to stop mode and restoring from stop mode must be performed at v dd = 2.3 v min. (f clk = 17 mhz) and v dd = 2.2 v min. (f clk = 13.5 mhz), respectively.
preliminary product information u15436ej1v0pm 71 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (2) in backup mode (t a = ?40 to +85 c, v ss = av ss = ev ss = v ss bu = v dd = av dd = ev dd = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr2 backup mode 1.6 2.7 v data retention current i dddr2 v dd bu = v dddr2 t.b.d. t.b.d. a backup supply voltage rise time t rvd2 t.b.d. s backup supply voltage fall time t fvd2 t.b.d. s mode setting time from reset to v dd t hvd2 t.b.d. ms mode release signal input time from v dd to reset t drel2 t.b.d. ms caution shifting to backup mode and restoring from backup mode must be performed at v dd = 2.3 v min. (f clk = 17 mhz) and v dd = 2.2 v min. (f clk = 13.5 mhz), respectively. setting stop mode 0 v note t hvd1 0.8ev dd 0.2ev dd v dd , ev dd , av dd v dd bu reset (input) t fvd2 t hvd2 t drel2 v dddr2 t hvd2 note shifting to backup mode and restoring from backup mode must be performed at v dd = 2.3 v min. (f clk = 17 mhz) and v dd = 2.2 v min. (f clk = 13.5 mhz), respectively.
preliminary product information u15436ej1v0pm 72 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y ac characteristics ac test input measurement points (v dd , av dd , ev dd , v dd bu) v dd 0 v v ih v il v ih v il measurement points ac test output measurement points v oh v ol v oh v ol measurement points load conditions dut (device under test) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, reduce the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
preliminary product information u15436ej1v0pm 73 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y clock timing (1) operating conditions (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.3 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit x1 input cycle 58.8 ns xt1 input cycle t cyx <1> 28.5 s x1 input high-level width 26.4 ns xt1 input high-level width t wxh <2> 12.8 s x1 input low-level width 26.4 ns xt1 input low-level width t wxl <3> 12.8 s x1 input rise time t xr <4> 0.5 (t cyx ? t wxh ? t wxl ) ns x1 input fall time t xf <5> 0.5 (t cyx ? t wxh ? t wxl ) ns clkout output cycle t cyk <6> 58.8 ns 16 s clkout high-level width t wkh <7> 0.5t cyk ? 5ns clkout low-level width t wkl <8> 0.5t cyk ? 5ns clkout rise time t kr <9> 5 ns clkout fall time t kf <10> 5 ns remark ensure that the duty for the x1 and xt1 input waveforms is between 45% and 55%. (2) operating conditions (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit x1 input cycle t.b.d. ns xt1 input cycle t cyx <1> t.b.d. s x1 input high-level width t.b.d. ns xt1 input high-level width t wxh <2> t.b.d. s x1 input low-level width t.b.d. ns xt1 input low-level width t wxl <3> t.b.d. s x1 input rise time t xr <4> t.b.d. ns x1 input fall time t xf <5> t.b.d. ns clkout output cycle t cyk <6> t.b.d. t.b.d. clkout high-level width t wkh <7> t.b.d. ns clkout low-level width t wkl <8> t.b.d. ns clkout rise time t kr <9> t.b.d. ns clkout fall time t kf <10> t.b.d. ns remark ensure that the duty for the x1 and xt1 input waveforms is between 45% and 55%.
preliminary product information u15436ej1v0pm 74 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y clock timing x1, xt1 (input) clkout (output) <2> <4> <5> <1> <3> <7> <9> <10> <8> <6>
preliminary product information u15436ej1v0pm 75 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y bus timing (1) multiplexed bus mode (a) clkout asynchronous: in multiplexed bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb )t sast <11> 0.5t ? 15 ns address hold time (from astb )t hsta <12> 0.5t ? 15 ns delay time from rd to address float t frda <13> 2 ns data input setup time from address t said <14> (2 + n)t ? 25 ns data input setup time from rd t srid <15> (1 + n)t ? 25 ns delay time from astb to rd , wrm t dstrdwr <16> 0.5t ? 15 ns data input hold time (from rd )t hrdid <17> 0 ns address output time from rd t drda <18> (1 + i)t ? 15 ns delay time from rd, wrm to astb t drdwrst <19> 0.5t ? 15 ns delay time from rd to astb t drdst <20> (1.5 + i)t ? 15 ns rd, wrm low-level width t wrdwrl <21> (1 + n)t ? 15 ns astb high-level width t wsth <22> t ? 15 ns data output time from wrm t dwrod <23> 15 ns data output setup time (to wrm )t sodwr <24> (1 + n)t ? 20 ns data output hold time (from wrm )t hwrod <25> t ? 15 ns t sawt1 <26> n 1 1.5t ? 25 ns wait setup time (to address) t sawt2 <27> n 1 (1.5 + n)t ? 25 ns t hawt1 <28> n 1 (0.5 + n)t ns wait hold time (from address) t hawt2 <29> n 1 (1.5 + n)t ns t sstwt1 <30> n 1t ? 25 ns wait setup time (to astb ) t sstwt2 <31> n 1 (1 + n)t ? 25 ns t hstwt1 <32> n 1ntns wait hold time (from astb ) t hstwt2 <33> n 1 (1 + n)t ns hldrq high-level width t whqh <34> t + 10 ns hldak low-level width t whal <35> t ? 15 ns delay time from hldak to bus output t dhac <36> ? 3ns delay time from hldrq to hldak t dhqha1 <37> 1.5t (2n + 7.5)t + 25 ns delay time from hldrq to hldak t dhqha2 <38> 0.5t 1.5t + 25 ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. m = 0, 1 4. i: number of idle states inserted after the read cycle (0 or 1). 5. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
preliminary product information u15436ej1v0pm 76 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (b) clkout synchronous: in multiplexed bus mode (t a = ?40 to +85c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <39> 0 19 ns delay time from clkout to address float t fka <40> ?12 7 ns delay time from clkout to astb t dkst <41> ?12 7 ns delay time from clkout to rd, wrm t dkrdwr <42> ?5 14 ns data input setup time (to clkout )t sidk <43> 15 ns data input hold time (from clkout )t hkid <44> 5 ns data output delay time from clkout t dkod <45> 19 ns wait setup time (to clkout )t swtk <46> 15 ns wait hold time (from clkout )t hkwt <47> 5 ns hldrq setup time (to clkout )t shqk <48> 15 ns hldrq hold time (from clkout )t hkhq <49> 5 ns delay time from clkout to bus float t dkf <50> 19 ns delay time from clkout to hldak t dkha <51> 19 ns remarks 1. m = 0, 1 2. the values in the above specifications are values for when clocks with a 1:1 duty ratio are input from x1.
preliminary product information u15436ej1v0pm 77 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y read cycle (clkout synchronous/asynchronous, 1 wait): in multiplexed bus mode clkout (output) a16 to a23 (output), a0 to a15 (output) ad0 to ad15 (i/o) astb (output) rd (output) wait (input) t1 t2 tw t3 <39> <40> <41> <11> <42> <19> <18> <20> <16> <30> <46> <32> <31> <33> <26> <28> <27> <29> <47> <46> <47> <15> <21> <17> <41> <14> <43> <44> address hi-z <13> <42> <12> <22> remark wr0 and wr1are high level. data
preliminary product information u15436ej1v0pm 78 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y write cycle (clkout synchronous/asynchronous, 1 wait): in multiplexed bus mode clkout (output) a16 to a23 (output), a0 to a15 (output) ad0 to ad15 (i/o) astb (output) wr0 (output), wr1 (output) wait (input) t1 t2 tw t3 <39> <45> <41> <11> <42> <19> <25> <16> <30> <46> <32> <31> <33> <26> <28> <27> <29> <47> <46> <47> <24> <21> <22> <12> <41> data address <23> <42> remark rd is high level.
preliminary product information u15436ej1v0pm 79 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y bus hold: in multiplexed bus mode clkout (output) hldrq (input) hldak (output) a16 to a23 (output) a0 to a15 (output) ad0 to ad15 (i/o) astb (output) rd (output), wr0 (output), wr1 (output) <48> <49> <51> <36> <35> <37> <38> <48> <51> <34> th th th ti hi-z hi-z hi-z data hi-z <50>
preliminary product information u15436ej1v0pm 80 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (2) in separate bus mode (a) read cycle (clkout asynchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to rd )t sard <52> 0.5t ? 15 ns address hold time (from rd )t hard <53> 2 ns rd low-level width t wrdl <54> (1.5 + n) t ? 10 ns data setup time (to rd )t sisd <55> 20 ns data hold time (from rd )t hisd <56> 0 ns data setup time (to address) t said <57> (2 + n) t ? 25 ns t srdwt1 <58> 0.5t ? 20 ns wait setup time (to rd ) t srdwt2 <59> (0.5 + n) t ? 20 ns t hrdwt1 <60> 0.5t ns wait hold time (from rd ) t hrdwt2 <61> (0.5 + n) t ns t sawt1 <62> t ? 20 ns wait setup time (to address) t sawt2 <63> (1 + n) t ? 20 ns t hawt1 <64> t ns wait hold time (from address) t hawt2 <65> (1 + n) t ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in bus cycle the sampling timing changes when a programmable wait is inserted. 3. the values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from x1. (b) read cycle (clkout synchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <66> 0 19 ns data input setup time (to clkout )t sisdk <67> 15 ns data input hold time (from clkout )t hkisd <68> 5 ns delay time from clkout to rd t dksr <69> 0 19 ns wait setup time (to clkout )t swtk <70> 15 ns wait hold time (from clkout )t hkwt <71> 5 ns remark the values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from x1.
preliminary product information u15436ej1v0pm 81 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y (c) write cycle (clkout asynchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to wrm )t saw <72> t ? 15 ns address hold time (from wrm )t haw <73> 0.5t ? 10 ns wrm low-level width t wwrl <74> (0.5 + n) t ? 10 ns data output time from wrm t dosdw <75> ? 5ns data setup time (to wrm )t sosdw <76> (0.5 + n) t ? 10 ns data hold time (from wrm )t hosdw <77> 0.5t ? 10 ns data setup time (to address) t saod <78> t ? 25 ns t swrwt1 <79> 20 ns wait setup time (to wrm ) t swrwt2 <80> nt ? 20 ns t hwrwt1 <81> 0 ns wait hold time (from wrm ) t hwrwt2 <82> nt ns t sawt1 <83> t ? 20 ns wait setup time (to address) t sawt2 <84> (1 + n) t ? 20 ns t hawt1 <85> t ns wait hold time (from address) t hawt2 <86> (1 + n) t ns remarks 1. m = 0, 1 2. t = 1/f cpu (f cpu : cpu operation clock frequency) 3. n: number of wait clocks inserted in bus cycle the sampling timing changes when a programmable wait is inserted. 4. the values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from x1. (d) write cycle (clkout synchronous): in separate bus mode (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address, cs t dksa <87> 0 19 ns delay time from clkout to data output t dksd <88> 0 19 ns delay time from clkout to wrm t dksw <89> 0 19 ns wait setup time (to clkout )t swtk <90> 15 ns wait hold time (from clkout )t hkwt <91> 5 ns remarks 1. m = 0, 1 2. the values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from x1.
preliminary product information u15436ej1v0pm 82 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y read cycle (clkout asynchronous, 1 wait): in separate bus mode clkout (output) t1 <57> hi-z hi-z <52> <54> <61> <59> <60> <58> <62> <64> <63> <65> <56> <55> <53> tw t2 rd (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input)
preliminary product information u15436ej1v0pm 83 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y read cycle (clkout synchronous, 1 wait): in separate bus mode clkout (output) t1 <69> <70> <71> <70> <71> <66> <69> <67> <68> hi-z hi-z tw t2 rd (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) <66>
preliminary product information u15436ej1v0pm 84 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y write cycle (clkout asynchronous, 1 wait): in separate bus mode clkout (output) t1 <78> <72> <75> <74> <82> <80> <81> <79> <83> <85> <84> <86> <77> <76> <73> tw t2 wr0, wr1 (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) hi-z hi-z
preliminary product information u15436ej1v0pm 85 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y write cycle (clkout synchronous, 1 wait): in separate bus mode clkout (output) t1 <88> <89> <91> <90> <89> tw t2 wr0, wr1 (output) cs0 to cs3 (output) a0 to a23 (output) ad0 to ad15 (i/o) wait (input) <87> <87> <91> <90> <88> hi-z hi-z
preliminary product information u15436ej1v0pm 86 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y reset/interrupt timing (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit reset high-level width t wrsh <92> 500 ns reset low-level width t wrsl <93> 500 ns nmi high-level width t wnih <94> 500 ns nmi low-level width t wnil <95> 500 ns intpn high-level width t with <96> n = 0 to 6 (analog noise elimination) 500 ns intpn low-level width t witl <97> n = 0 to 6 (analog noise elimination) 500 ns remark t = 1/f xx reset <92> <93> reset (input) interrupt <94> <95> nmi (input) <96> <97> intpn (input) remark n = 0 to 6
preliminary product information u15436ej1v0pm 87 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y timer timing (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit n = 0, 1 2t + 20 ns tin high-level width n = 2 to 5 40 ns n = 0, 1 2t + 20 ns tin low-level width n = 2 to 5 40 ns tclrn high-level width n = 0, 1 2t + 20 ns tclrn low-level width n = 0, 1 2t + 20 ns intpnm high-level width t with nm = 00, 01, 10, 11 2t + 20 ns intpnm low-level width t witl nm = 00, 01, 10, 11 2t + 20 ns remark t = 1/f xx
preliminary product information u15436ej1v0pm 88 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y csi timing (1) master mode (t a = ?40 to +85c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle time t kcy1 <98> output 200 ns sckn high-/low-level width t kh1 , t kl1 <99> output t kcy1 /2 ? 10 ns sin setup time (to sckn )t sik1 <100> 30 ns sin hold time (from sckn )t ksi1 <101> 30 ns delay time from sckn to son output t kso1 <102> 30 ns remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) (2) slave mode (t a = ?40 to +85c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle time t kcy2 <98> output 200 ns sckn high-/low-level width t kh2 , t kl2 <99> output 90 ns sin setup time (to sckn )t sik2 <100> 50 ns sin hold time (from sckn )t ksi2 <101> 50 ns delay time from sckn to son output t kso2 <102> 50 ns remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) <101> <102> <100> <98> <99> hi-z hi-z <99> remark n = 0 to 3 (v850es/sa2), n = 0 to 4 (v850es/sa3) sckn (i/o) sin (input) son (output) input data output data
preliminary product information u15436ej1v0pm 89 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y i 2 c bus mode ( pd703201y, 703204y, 70f3201y, 70f3204y only) (t a = ? 40 to +85 c, v dd = av dd = ev dd = v dd bu = 2.2 to 2.7 v, v ss = av ss = ev ss = v ss bu = 0 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scl clock frequency f clk 0 100 0 400 khz bus-free time (between stop/start conditions) t buf <103> 4.7 ? 1.3 ? s hold time note 1 t hd:sta <104> 4.0 ? 0.6 ? s scl clock low-level width t low <105> 4.7 ? 1.3 ? s scl clock high-level width t high <106> 4.0 ? 0.6 ? s setup time for start/restart conditions t su:sta <107> 4.7 ? 0.6 ? s cbus compatible master 5.0 ??? s data hold time i 2 c mode t hd:dat <108> 0 note 2 ? 0 note 2 0.9 note 3 s data setup time t su:dat <109> 250 ? 100 note 4 ? ns sda and scl signal rise time t r <110> ? 1,000 20 + 0.1cb note 5 300 ns sda and scl signal fall time t f <111> ? 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <112> 4.0 ? 0.6 ? s pulse width with spike suppressed by input filter t sp <113> ?? 050ns capacitance load of each bus line cb ? 400 ? 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda signal (at v ihmin. . of scl signal) in order to occupy the undefined area at the falling edge of scl. 3. if the system does not extend the scl signal low hold time (t low ), only the maximum data hold time (t hd : dat ) needs to be satisfied. 4. the high-speed-mode i 2 c bus can be used in a normal-mode i 2 c bus system. in this case, set the high- speed-mode i 2 c bus so that it meets the following conditions. ? if the system does not extend the scl signal's low state hold time: t su : dat 250 ns ? if the system extends the scl signal's low state hold time: transmit the following data bit to the sda line prior to releasing the scl line (t rmax. + t su : dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf)
preliminary product information u15436ej1v0pm 90 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y i 2 c bus mode ( pd703201y, 703204y, 70f3201y, 70f3204y only) stop condition stop condition start condition restart condition scl (i/o) sda (i/o) <105> <111> <111> <110> <110> <108> <109> <107> <104> <103> <104> <113> <112> <106> a/d converter (t a = ? 40 to +85 c, v dd = av dd = av ref0 = 2.2 to 2.7 v, av ss = v ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 t.b.d. %fsr conversion time t conv t.b.d. s zero-scale error note 1 t.b.d. %fsr full-scale error note 1 t.b.d. %fsr integral linearity error note 2 t.b.d. lsb differential linearity error note 2 t.b.d. lsb analog reference voltage av ref av ref0 = av dd 2.2 2.7 v analog input voltage v ian av ss av ref v av ref0 current ai ref0 t.b.d. a av dd power supply current ai dd t.b.d. ma notes 1. excluding quantization error ( 0.05 %fsr) 2. excluding quantization error ( 0.5 lsb) remark lsb: least significant bit fsr: full scale range
preliminary product information u15436ej1v0pm 91 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y d/a converter (t a = ? 40 to +85 c, v dd = av dd = av ref1 = 2.2 to 2.7 v, av ss = v ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 888bit overall error note load conditions: 2 m ? , 30 pf av ref1 = v dd t.b.d. %fsr settling time t.b.d. s output resistance t.b.d. k ? analog reference voltage av ref av ref1 = v dd 2.2 2.7 v av ref1 current av ref1 per channel t.b.d. ma note excludes quantization error ( 0.05%fsr).
preliminary product information u15436ej1v0pm 92 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 21. package drawings 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
preliminary product information u15436ej1v0pm 93 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y 121-pin plastic fbga (12x12) item millimeters d 12.00 0.10 e 12.00 0.10 0.10 p121f1-80-ea6 index mark a w 0.20 a2 a1 a 1.13 e 0.80 1.48 0.10 0.35 0.06 x y 0.20 y1 1.20 zd 1.20 ze 0.08 ze a2 a1 b zd b a s s wa s wb s y1 se y 13 12 11 10 9 8 7 6 5 4 3 2 1 nmlk jhgfedcba s xab m e d b 0.50 + 0.05 ? 0.10
preliminary product information u15436ej1v0pm 94 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y appendix development tools (1) hardware product name description in-circuit emulator ie-v850es- note (provisional name) in-circuit emulator for v850es in-circuit emulator option board ie-703204-mc-em1 note (provisional name) option board to emulate v850es/sa2, v850es/sa3 peripheral functions in combination with in-circuit emulator v850es/sa2 note emulation probe for 100-pin lqfp emulation probe v850es/sa3 note emulation probe for 121-pin fbga power supply unit ie-70000-mc-ps-b power supply for in-circuit emulator ie-70000-cd-if-a interface board for connection to pc (for pcmcia) pc interface board ie-70000-pci-if interface board for connection to pc (for pci) flash programmer note flash programmer for writing a program to a single- power-supply flash memory product. v850es/sa2 note program adapter for 100-pin lqfp program adapter v850es/sa3 note program adapter for 121-pin fbga note under development (2) software product name description compiler ca850 c compiler compliant with ansi-c debugger id850 debugger used in combination with in-circuit emulator real-time os rx850 real-time os compliant with itron specifications v850es/sa2 df703201 note definition file for v850es/sa2 device file v850es/sa3 df703204 note definition file for v850es/sa3 note under development
preliminary product information u15436ej1v0pm 95 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y [memo]
preliminary product information u15436ej1v0pm 96 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. caution purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850 family, v850es/sa2, and v850es/sa3 are trademarks of nec corporation. tron stands for the real-time operating system nucleus. itron is an abbreviation of industrial tron.
preliminary product information u15436ej1v0pm 97 pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
pd703201, 703201y, 703204, 703204y, 70f3201, 70f3201y, 70f3204, 70f3204y the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed: pd70f3201, 70f3201y, 70f3204, 70f3204y the customer must judge the need for license: pd703201, 703201y, 703204, 703204y ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98. 8

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